The present invention relates to the field of instruction-controlled digital computers and specifically to the interconnection of and the priority determinations among the units forming the data processing system.
High-speed data processing systems generally include a plurality of units interconnected over one or more buses. Typical units connected by a bus include one or more storage units for storing data and instructions, one or more input/output devices, a console for operator and other communication with the system, and a processor for instruction handling and execution.
When the units of a system are interconnected by common buses, a need arises for controlling access to the buses. When more than one unit may request an operation using the bus, a priority determination must be made so as to determine the order in which units will be able to obtain access to the bus.
Various priority techniques have been known. For example, some systems employ a serial priority technique. In the serial priority technique, the units in a system are interconnected by a "daisy chain" which connects in series from the highest priorty unit to the lowest priorty unit. The "daisy chain" circuitry operates such that a unit requesting access must be enabled by its own stage in the daisy chain circuitry. If a unit of higher priority is requesting access, the higher priority unit energizes the daisy chain circuit so that all the lower-order units are disabled and cannot obtain access. Whenever there is no higher priority unit having access, than a unit requesting access obtains access and energizes the "daisy chain" circuitry thereby inhibiting all units of lower priority from obtaining access.
Serial priority techniques work well in many environments, but they present a problem in that each unit connected into the serial priority circuitry adds an additional stage of delay to the operation of the priority circuitry. For a small number of units in the priority scheme, the delay contributed by each stage is small and usually can be tolerated. Where many units are to be connected into the priority scheme, however, the serial priority schemes become undesirable because of the amount of delay attendant its operation.
Serial priority techniques have other drawbacks. For example, when it is desired to have different levels of priority, serial priority techniques are generally inadequate. In order to overcome the limitations of serial priority schemes, some data processing systems have employed a centralized priority distributor. Such a centralized priority distributor receives inputs from and delivers outputs to each unit in the priority configuration. Such a centralized priority distributor, however, is difficult to implement in modular systems where the number of units in the priority configuation is large or is intended to increase. Generally, separate interconnections are required between a centralized priority distributor and each unit in the configuration. The need to make separate connections for each unit is undesirable and makes modularized systems more difficult.
In accordance with the above background, there is a need for an it is an objective of the present invention to provide improved priority circuitry for use within data processing systems.